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RISC-V
 | |
| Designer | University of California, Berkeley |
|---|---|
| Bits | 32, 64, 128 |
| Introduced | 6 August 2014[1] |
| Version | |
| Design | RISC |
| Type | Load–store |
| Encoding | Variable |
| Branching | Compare-and-branch |
| Endianness | Little[2]: 9 [a] |
| Page size | 4 KiB |
| Extensions |
|
| Open | Yes, royalty free |
| Registers | |
| General-purpose |
|
| Floating point |
|
RISC-V[b] (pronounced "risk-five"[2]: 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 2019.[5][6] Like several other RISC ISAs, e.g. Amber (ARMv2) or OpenRISC, RISC-V is offered under royalty-free open-source licenses.[7] The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD License.
Mainline support for RISC-V was added to the Linux 5.17 kernel, in 2022, along with its toolchain.[8] In July 2023, RISC-V, in its 64-bit variant called riscv64,[9] was included as an official architecture of Linux distribution Debian, in its unstable version.[10] The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA."[11]
Some RISC-V International members, such as SiFive, Andes Technology, Synopsys, Alibaba's Damo Academy, Raspberry Pi, and Akeana,[12][13] are offering or have announced commercial systems on a chip (SoCs) that incorporate one or more RISC-V compatible CPU cores.[14]
- ^ Asanović, Krste; Patterson, David A. (6 August 2014). Instruction Sets Should Be Free: The Case For RISC-V (PDF). EECS Department, University of California, Berkeley. UCB/EECS-2014-146.
- ^ a b c d Cite error: The named reference
isa20191213was invoked but never defined (see the help page). - ^ Cite error: The named reference
priv-isawas invoked but never defined (see the help page). - ^ Urquhart, Roddy (29 March 2021). "What Does RISC-V Stand For? A brief history of the open ISA". Systems & Design: Opinion. Semiconductor Engineering.
- ^ "About RISC-V". RISC-V International.
- ^ "RISC-V To Move HQ to Switzerland Amid Trade War Concerns". EE Times Europe. 28 November 2019.
- ^ "Frequently Asked Questions (FAQ) – RISC-V International". Retrieved 20 August 2024.
- ^ "Linux 5.17 Adds Support For "The First Usable, Low-Cost RISC-V Platform" | Michael Larabel, Phoronix – RISC-V International". 2022. Retrieved 20 August 2024.
- ^ "RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
- ^ "riscv64 is now an official architecture". lists.debian.org. Retrieved 13 August 2024.
- ^ "RISC-V - Debian Wiki". wiki.debian.org. Retrieved 13 August 2024.
- ^ Anton Shilov (20 March 2024). "Alibaba claims it will launch a server-grade RISC-V processor this year". Tom's Hardware. Retrieved 19 August 2024.
- ^ Connatser, Matthew (13 August 2024). "Akeana debuts RISC-V CPU designs on $100M budget, longs for an Arm wrestle". The Register. Retrieved 19 August 2024.
- ^ Cite error: The named reference
:5was invoked but never defined (see the help page).
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